Improvement of performance of MISFET has been achieved by a scaling-down technique. However, because the scaling-down technique is approaching the limit, the technique of improving the performance of MISFET except for the scaling-down technique is studied. The use of a substrate except for a Si substrate which has electron or hole mobility higher than that of Si, for example, the use of a SiGe substrate or a Ge substrate is studied. Also studied is a technique embedding SiGe or Ge in a source/drain region, and applying a distortion to Si channel, thereby improving the carrier mobility in the Si channel.
A reverse leakage current of a pn junction or a Schottky junction of the source/drain region is increased as a semiconductor band gap Eg is decreased. Si and Ge have band gaps Eg of 1.1 and 0.66 eV at a room temperature (20° C.), respectively. Therefore, the large amount of reverse leakage current of the junction is cited as one of problems with MISFET formed on the SiGe or Ge substrate. Additionally, sometimes various defects are introduced into the semiconductor substrate near the junction during the MISFET forming process. The junction leakage current is further increased according to the amount of defect in a depletion layer near the junction, which worsens the problem.
Examples of the defect generated in the semiconductor crystal include a point defect such as a dangling bond, a dislocation, and a stacking fault. Recently it is reported that the introduction of S (sulfur) is an effective technique of compensating the defect generated in a NiGe/Ge interface. In the Schottky junction formed in the Ge substrate using NiGe, Fermi level pinning (FLP) can be solved by segregating sulfur in a metal/semiconductor interface (K. Ikeda, Y. Yamashita, N. Sugiyama, N. Taoka and S. Takagi, Applied Physics Letters, 88, 152115 (2006)). It is believed that FLP is generated due to the defect existing in the metal/semiconductor interface, and it is believed that sulfur compensates the defect existing in the metal/semiconductor interface to solve the pinning.
Desirably a junction depth Xj of the source/drain region is made shallow to improve controllability by a gate electrode of MISFET. In the Si substrate, it is known that the junction depth Xj can be made shallow by ion implantation of a dopant after the Si substrate is transformed into an amorphous state by Ge ion implantation. However, a technique of forming the shallow junction depth Xj is not known yet in the Ge substrate.